1. Field of the Invention
The present invention relates to packaging of semiconductor dice. More particularly, the present invention relates to improved processes for separating and coating semiconductor dice at the wafer level to form individual chip-scale packages.
2. State of the Art
A solid-state electronic device in the form of a semiconductor die or chip is typically manufactured of materials such as silicon, germanium, gallium arsenide or indium phosphide. Circuitry is formed on an active surface of the semiconductor die and may include further circuit levels within the die itself. Bond pads are also formed on the active surface to provide electrical contacts for the semiconductor die circuitry. Due to the materials used and the intricate nature of construction, a semiconductor die is highly susceptible to physical damage or contamination from environmental conditions such as moisture.
Conventionally, a semiconductor die has been protected by mounting it within a plastic, metal or ceramic package that prevents physical contact with the die and provides hermetic sealing. The package also includes conductive leads for attaching the die bond pads to outside electrical connections. The materials required for this packaging approach increase cost, while resulting in a larger device size that takes up valuable real estate when mounted to a carrier substrate. The added lead structure may also influence processing speed, and further presents opportunities for moisture incursion at interfaces between the conductive leads and other packaging materials.
Some efforts to reduce the size and cost of these electronic devices have resulted in doing away entirely with the above-described packaging materials. Instead, the semiconductor die is protected by forming what is commonly referred to as a chip-scale package (CSP). In a typical example of this packaging method, a protective coating is added to surfaces of the semiconductor die itself, and conductive bumps are formed over the die bond pads using a variety of known techniques such as screen printing or by ball bumping with wire-bonding equipment. The bumps may then be electrically connected to circuitry on a carrier substrate by tape automated bonding (TAB), or may be directly attached thereto by mounting the semiconductor die in a flip-chip fashion on the carrier substrate. Alternatively, the conductive bumps may be omitted, and the CSP may be attached to a carrier substrate using conventional wire bonds.
Materials used for formation of the protective coating on the surfaces of the semiconductor die may include, for example, silicon nitride (SiN), silicon dioxide (SiO2), or other materials like epoxy or polymers. In the prior art, these coatings would be deposited on the active and passive surfaces of a wafer containing an array of semiconductor die locations, and the wafer would subsequently be singulated to provide individual semiconductor dice. A resulting semiconductor die using this method suffers from the fact that its sides, and specifically the sides of its active surface, are left exposed after the wafer singulation. The possibility remains, therefore, that moisture may enter the sides of the die and damage nearby circuitry.
In order to rectify these shortcomings, various attempts have been made to add additional protective coatings to the sides of a semiconductor die. One approach to coating side surfaces has been to first form cuts or channels in the active surface of a wafer to at least partially expose the sides of each semiconductor die, and then deposit the protective coating onto the wafer. In this manner, the protective coating material enters the channels surrounding each die, and subsequent singulation of the wafer along the channels provides semiconductor dice having active surface and partial side surface coatings. Examples of such a process are disclosed in U.S. Pat. No. 5,742,094 to Ting, U.S. Pat. No. 5,933,713 to Farnworth and U.S. Pat. No. 5,956,605 to Akram et al. While these methods provide at least partial side surface protective coatings, they may require additional processing of the semiconductor dice on an individual basis to completely coat the sides or back of the semiconductor dice.
Another problem with these methods is that formation of the channels in the active surface of the wafer is typically accomplished using processes that may cause damage to the semiconductor material on the side surfaces of a completed semiconductor die. The channels may be formed, for instance, by cutting with a dicing saw or a laser. When the channels are cut using a dicing saw, diamond particles in the saw may leave nicks and scratches in the cutting surface. Similarly, when the channels are formed by laser cutting, heat from the laser energy may negatively affect the semiconductor material along the channel surfaces, leaving what is sometimes referred to as a heat-affected zone (HAZ). These material defects may result in crack propagation from stress concentrations that will damage the active circuitry adjacent to the channels, or may degrade the semiconductor material to a point where it exhibits current leakages or other undesirable electrical properties. This problem is further aggravated by the fact that the area available for cutting between adjacent semiconductor dice in a wafer, sometimes referred to as a street, is constantly being decreased to save space. For example, while wafers have previously typically been formed with 150-micron street widths, the current manufacturing technology involves forming narrower streets on the order of 100 microns. The reduction in width means that any material defects in the surfaces of channels will be closer to the active circuitry of a semiconductor die and will, therefore, be more likely to cause damage.
In view of the above, it would be desirable to have an improved method for separating and coating the surfaces of semiconductor dice at the wafer level.